Senior ASIC Design Engineer

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Job Title: Senior ASIC Design Engineer

Location: Cambridge, CB4.

Salary Package: C£60K + Stock Options.

Key Skills: RTL (Verilog / VHDL), Verification (UVM, System Verilog), Hardware Synthesis Tools (Synopsys, Cadence), Simulation Tools.

A fast growing Cambridge start-up, specialists in Image Processing and Computational Photography, seeks an academically strong Senior Hardware Design Engineer with expertise in RTL (VHDL / Verilog) and industry standard Verification methodologies.

The successful Senior ASIC Design Engineer will take responsibility for the implementation of Algorithms and functional blocks for ASIC synthesis; will undertake System integration, functional debugging of implemented blocks and algorithms as well as block level verification.

Key Skills & Experience required:

                                                   Hardware Design skills in RTL ( VHDL, Verilog ).

                                                   Verification methodologies.

                                                   Hardware Synthesis Tools ( Synopsys, Cadence etc.)

                                                   Simulation Tools such as Modelsim, nc-sim, Questa, VCS.

                                                   Good Python, C/C++ skills and an understanding of Matlab.

                                                   Block design, block level verification, timing closure, size & speed optimization.

                                                   Memory subsystems, AXI and system integration.