Digital ASIC Design Engineer
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Based in Oregon, our leading RISC-V client is seeking a Digital ASIC Design Engineer to join their CPU team.
Our client is ranked among the world’s top IP companies and has multiple opportunities for Digital ASIC Design Engineers to join their CPU team. As RISC-V is poised to challenge ARM/X86, there is huge growth potential in various market segments including 5G, AI and machine learning.
The Digital ASIC Design Engineer will work as part of a cohesive team focusing on CPU hardware design, looking at the balance of performance, area, and power, and covering complex vector or floating-point maths, load-store units, coherent memory access or multi-core debug architecture.
Requirements include:
- Eligibility to work in the US, either US passport or Green Card (H1-B sponsorship cannot currently be sponsored)
- A Bachelors or Masters degree in Electronic Engineering or related field
- A strong background within RTL Design and Verification with VHDL / Verilog / SystemVerilog
- An understanding of processor architecture is desirable
For details, please contact Caroline Pye.