Design Verification Engineer
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Design Verification Engineer
State of Oregon
I am seeking a Design Verification Engineer to join a leading RISC-V Semiconductor client based in Oregon. This role can be office-based, or remote from within the US.
My client is ranked among the world’s top IP companies and has multiple opportunities for Digital Verification Engineers to join their CPU team. As RISC-V is poised to challenge ARM/X86, there is huge growth potential in various market segments including 5G, AI and machine learning. Design Verification Engineers will work as part of a cohesive team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.
As a senior member of this team, you will help guide verification methodologies, analyse problems and participate in engineering discussions and be expected to drive analysis and propose directions.
Responsibilities
- Analyse CPU architecture and microarchitecture implementations, and devising best methods to verify them.
- Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports
- Hands-on verification work including verification regression management, debugging and bug-reports
- Experience using Verilog, System Verilog
- Experience of CPU architecture
- Experience coding in assembly languages
- Experience in UVM, formal, coverage grading, coverage analysis, bug tracking
For more information, please contact Rachel Mason.
