Formal Verification Engineer

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Remote - United States or Canada

Must have US/Canadian working rights.

I am seeking a Formal Verification Engineer to join a leading RISC-V Semiconductor client based in the United States of America. This role can be office-based, or remote from within the US or Canada.

My client is ranked among the world’s top IP companies and has an opportunity for a Formal Verification Engineer to join their CPU team. As RISC-V is poised to challenge ARM/X86, there is huge growth potential in various market segments including 5G, AI and machine learning. Design Verification Engineers will work as part of a cohesive team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.

Responsibilities

• Communication with peers to discuss technical details.
• Analyse CPU architecture and microarchitecture implementations and devising best methods to verify them.
• Identify and resolve engineering issues ranging from functional verification, code coverage, formal proofs, verification reports.
• Hands-on verification work including verification regression management, debugging and bug-reports.
• Provide technical guidance to junior members of the team.
• Technical documentation

• Over 3 years of applicable work experience
• Experience using Verilog, System Verilog
• Strong knowledge using Unix and scripting languages such as make, shell, perl or python
• Experience in Formal Property Verification
• Experience in Formal Coverage Analysis
• Experience in the use of Formal tools such as JasperGold of FPV
• Experience of CPU architecture
• Experience coding in assembly languages
• Experience in UVM, formal, coverage grading, coverage analysis, bug tracking

For more information contact Rachel Mason at IC Resources.