Design Verification Manager

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Hybrid model but onsite requirement is needed weekly.

Senior Engineer or Junior Manager - experience with team leading required.

This is an exciting opportunity for a Design Vrifiction Manager to join part of the VLSI team, which is part of my client’s worldwide CPU development team. You will join a rapidly growing organisation, and you will get the opportunity to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.

As a leader of this team, you will define verification methodologies, analyse problems, participate in engineering discussions and drive analysis and propose directions.

You will mentor junior members of the team and to be successful should have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.

Responsibilities

• Mentor/teach other verification members in their approaches.
• Track schedule and project status.
• Communication with team members to discuss technical details.
• Analyse CPU architecture and microarchitecture implementations and devising best methods to verify them.
• Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports.
• Hands-on verification work including verification regression management, debugging and bug-reports.

• Proven track record for verifying designs to tape out quality.
• Experience using Verilog, System Verilog, UVM, coverage analysis, formal.
• Strong mastery using Unix and scripting languages such as make, shell, perl or python.
• Experience of CPU.
• Experience coding in assembly languages.
• Cross-site or multi-time zone experience.