Senior Digital IC Verification Engineer
Recruiter
IC Resources
Listed on
24th April 2023
Location
Delft
Salary/Rate
£50000 - £75000
Type
Permanent
Start Date
2022-12-20
This job has now expired please search on the home page to find live IT Jobs.
Working for a leading edge, innovative & deep-tech start-up, this is a fabless semiconductor company who have developed a world leading GNSS sensor chipset that has a unique, ultra-low power consumption solution which is going to disrupt the industry and take the market by storm! As Principal Digital IC Verification Engineer, you will be responsible for the digital frontend (RTL) verification and and post-layout simulation. This will include block/function simulation and unit level verification of digital functions on Mixed Signal ASICs, and doing post-layout simulation and working with physical design team on STA and logical issues. As an experienced senior digital verification engineer, you will be responsible for verification of digital IP blocks and simulation of Chip level post-layout within our upcoming SoCs. You will contribute to circuit design for next-generation products. The following will be your core responsibilities: Frontend ExpertiseRTL verification of digital circuits in Verilog.Simulation and verification of digital block implemented in RTL for various functions including control state machine digital signal processing (DSP), and multiple clock domain interface managementPost-layout simulation of complex mixed-signal SOCDevelop test benches and test cases for block-level functional verificationWork with backend/implementation teams to address synthesis, timing, DFT issues for ASIC implementationUnderstanding of all design integration activities like Lint, CDC, Synthesis & ECODefine verification and test plan, run regressions, reproduce, and debug functional and performance bugs.Backend Expertise
Understanding of backend design flow, including RTL synthesis, clock tree synthesis, scan and DFT insertion, place and route, and netlist verificationCollaborate with analog design engineers, CAD, systems engineering, test engineering and applications teams to ensure define optimal DFT, DFM features and achieve rapid silicon bring-up and time to production releaseAnalyze circuit for failure root cause analysis, investigate anomalous observations in silicon across various conditions, including PVT variations, and propose solutionsVerification of various IPs/Sub IPs integrated to top level SoCUnderstanding design synthesis and identify and fix timing issues for the Physical Design teamRequirements
B.Sc or higher in electronic engineering with 10-15 years of proven experience as a senior digital IC verification engineerASIC IP developmentSystem Verilog for IP / SOC Verification of digital ICs / ASIC IP or chipscomplex ASIC designs & architecture for advanced technology nodesVerification Metrics definition, Coverage analysis and debugging skills.Knowledge and experience on setting up an ASIC Verification environment, methodology and flow.vManager, vPlan and Regressions, etc.Digital Test Plan definition / creating / set-up test benchesscripting / coding skills - perl, shel, C/C++, python etc.mixed-signal product experience is a bonusFor more information, please contact Rob Hudson @ IC Resources!
