Digital Verification Engineer - Edinburgh

This a fantastic opportunity for a Verification Engineer to come and join the team in Edinburgh, working for one of the World leading providers of low power, mixed signal integrated circuits. You will be using advanced verification methodologies and concepts to complete your work, working closely with the design team.

Located in central eastern Scotland,Edinburgh is Scotland’s capital, it has a Historical background with Museums, Art Galleries and Cathedrals for you to visit. If that is not up your street it also has plenty of great food and stunning views for you to appreciate as well as great Universities and nightlife, perfect for the whole family!

Requirements:

• System Verilog for verification using advanced verification methodologies (preferably UVM or similar such as Specman-e, OVM, SystemC, etc.)
• Assertion based verification and Formal verification
• Familiar with either Verilog or VHDL RTL coding and ASIC design methodology
• Familiar with behavioural modelling of analog blocks
• Good knowledge of UNIX shell scripting, Perl, and TCL scripting
• Proven experience in writing verification plans and test bench development, simulation and debugging

• Expertise in Automotive ISO26262 standard and fault simulation
• Expert in constrained random verification and metric driven verification
• Expert in simulation and regressions tools e.g. Cadence Incisive, vManager, IMC

Contact Name: Jordan Browne
Reference: TJ/801/V-178860
Job ID: 3081791