BM Engineer

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I am looking for an excellent behavioral modeling (BM) engineer.

The job will require you to translate mixed signal schematics into SystemVerilog behavioral models for full chip DV simulations.

You will be working closely with the Analog, DV and Systems teams, helping debug various simulations.

 Minimum Qualifications

• Experience of 3+ in Real Number Modeling (RNM)/Behavioral Modeling (BM)
• Experience in SystemVerilog, Packages and User Defined Nettypes (UDN)
• Experience in Virtuoso Schematics tools
• knowledge in both Analog and Digital design
• Fluent English
• Highly motivated
• Learning abilities
• Good communication

• Work with external vendors
• Experience in both Synopsys and Cadence tools is an advantage
• SKILL programming experience