Digital IC Verification Engineer
Recruiter
IC Resources
Listed on
25th May 2023
Location
Modena
Salary/Rate
£30000 - £65000
Type
Permanent
Start Date
2022-12-20
This job has now expired please search on the home page to find live IT Jobs.
Working for a leader in power in power electronics, this is a great opportunity to join a growing team, as UVM verification engineer. Job duties:Developing test plans, tests and verification infrastructure using SV/UVM methodologyBuilding reusable bus functional models, monitors, checkers and scoreboardsPerforming coverage driven verification closurePerforming block level, multi-block level and system-level verificationPerforming Gate level simulationsPerforming Mixed Signal simulationsImplementing Regression testsPerforming Formal VerificationWorking closely with IC designers and post-silicon engineersQualifications and Background
Requirements:
Knowledge/experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbenches creationKnowledge/experience in scripting languages, such as Tcl and PythonSome knowledge of ASIC design flow and related verification stepsNice to have:
Some experience in digital RTL designKnowledge of UVM environments and classesSome experience with main EDA vendors simulators such as Questasim and XceliumKnowledge of DFT structures and test pattern generationSome experience in silicon validation/characterisationExperience working on Git.For more information, please contact Rob Hudson @ IC Resources
