Senior UVM Verification Lead (ASIC)
Recruiter
IC Resources
Listed on
25th May 2023
Location
Lausanne
Salary/Rate
£80000 - £120000
Type
Permanent
Start Date
2022-12-20
This job has now expired please search on the home page to find live IT Jobs.
New opportunity as Senior UVM Verification Lead - working for an exciting semiconductor scale-up company, based in the beautiful setting of Lausanne, overlooking lake Geneva. You will be working on the latest developments in high-speed communications, on products such as: SerDes, DSP, ethernet and PCIe. As Senior UVM Verification Lead, you will perform a hybrid role - with responsibilities for leading a small team, as well as maintaining hands on control of verification of ASIC IP products. Key Responsibilities:Act as verification lead on projectsProvide technical leadership & mentoringPrepare design verification plan based on design specificationsPlan and schedule projects , assign and track tasks for team membersDevelop design verification methodologies and implement standard debug flowsParticipate in design reviewsMaintain design verification environment and track & close design bugsWork with designers in verification and validation of circuit designsUtilise the latest techniques, tools, and technologies for design verification activities Skills
Excellent communication skills, strong team playerGood scripting techniques, experience with regression setup & management - TcL, pery, shel, python, cDeep understanding of simulation and verification environments, including debugging techniquesExperience with Gate Level Simulation flows and debug.Strong knowledge on Metrics-driven verification (incl. verification planning and coverage closure)Experienced with testbench development using the latest methodologiesExperience with 3rd party VIP usage and test development (a big plus) Experience
Bachelor's degree in electronics or micro-electronics or similar field7+ years’ experience in the semiconductor industryExperience in leading and managing a teamProven track record in verifying complex designs (preferably in high volume applications)Skilled in trade-offs between quality and scheduleExperience in constrained random testbench developmentFamiliarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageousExtensive digital verification background with some UVM experience, system verilog etc.Visa sponsorship can be offered Please contact Rob Hudson @ IC Resources for more information
