Analog IC Layout Engineer

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A Semiconductor start-up in the image sensor market is looking for an experienced Analog IC Layout Engineer to join their design team in Zurich. This is a young and dynamic team and you will be responsible for the Analog IC Layout of critical blocks for CMOS image sensor products in 40 - 65nm process from block level to chip level and tape out. As the successful Analog IC Layout Engineer you are industry degree qualified and have at least 5 years of experience in standard tools (Cadence, DRC, LVS, Calibre) including tape out experience and are able to work independently. Experience in Skill programming is beneficial. Candidate from within Switzerland will be preferred and applications from EU nationals will be considered.  For more information and to apply, please click APPLY NOW to be contacted for an initial discussion by Ane!