Senior Digital Verification Engineer

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Exciting new opportunity as Senior Design Verification Engineer to join the world leader in on-chip interconnect technology integration and deployment for SoCs.  Located in the beautiful outskirts of Paris, my client provides semiconductor intellectual property (IP) for some of the best known brands in the world - covering a wide range of applications from AI to cars, mobile phones, IoT, cameras, and SSD controllers.  As Senior Design Verification Engineer, you will be working with skilled engineers who are passionate about what they do - and want the same from you! As part of the role, you will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between.  Responsibilities:Advanced UVM based test bench development and debuggingDefining, documenting, developing and executing RTL verification test/coverage at system levelPerformance verification and power-aware verificationTriaging Regressions, Debugging RTL designs in Verilog and SystemVerilogHelp improve and refine verification process, methodology, and metricsUVM expertise on complex SoC projects from test bench development to verification closureExperience, Requirements and Qualifications:10 or more years of design and verification experience - interconnect verification experience is a bonusVerification flow enhancements using a scripting language such as Shell scripts, Python, TCL & JavaScriptStrong RTL (Verilog) and UVM/C test bench debugging skillsExperience integrating vendor provided VIPs for unit and system level verificationExperience with Arm AMBA protocolsThis opportunity involves high performance, low power designs on a highly visible projectEducation:MS degree in EE, CS, or equivalent preferred. BS degree minimum.