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Analog IC Layout Engineer

Premium Job From IC Resources
Recruiter: IC Resources
Listed on: 26th November 2020
Location: Delft
Salary/Rate: £40000 - £50000
Type: Permanent
Start Date: 2020-11-26

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A Semiconductor company with a focus on Power conversion and Sensor Interfacing is looking for an Analog IC Layout engineer who can take a leading role in creating complex IC layouts.  Your responsibilities will include the following:Communicate with design engineers on layout trade-offs as needed to build complex analog and mixed signal block level layouts in Sub-Micron CMOS technologiesDeliver high quality analog block layouts that meet stringent matching, performance, area and power requirements while conforming to all PDV design requirements and meet project milestone deadlinesRunning complete set of design verification tools available on block-level, Sub-System level, and top-level layoutsProvide accurate schedules for block level, top-level layout and integration and report to layout managerRecognise failure prone circuit and layout structures and propose mitigating actionsDebug and drive resolutions to Physical Design Kit issues, DRC/LVS/ERC improvements with respect to layoutsSolve problems while using a combination of technical skills, intuition, and creativityContribute ideas for improved productivity and automation of layout tasksRecognise apparent mistakes in the analog designPropose design changes when it benefits the layoutThe successful Analog IC Layout Engineer has the following qualifications and skills: BSc or MSc degree Electrical engineering, specialised in Micro-electronics3+ years’ experience creating custom analog/mixed-signal layouts at chip, block, and device levels in sub-micron CMOS technologiesExpertise with Cadence Virtuoso XL schematic driven layout design flow, Virtuoso Floor Planning, Constraint Driven Layout, and extraction flowsExpertise using Cadence verification suite (PVS-DRC, LVS, ERC); high proficiency with interpretation, debug, and understanding of resultsStrong experience with high performance analog layout techniques for device matching, common centroid layout, isolation, shielding, use of dummy devices, parasitic sensitivities, and also chip level electromigration, IR drop, self-heating, cross coupling capacitance and DFM practicesGood understanding of package needs and constraints with respect to chip levelLayout experience with analog on-top and digital on-top flows, including defining, directing, and reviewing layout team’s workProven capability at chip and block level in floor planning, power routing, ESD, physical design area estimates, effort/schedule estimationsUnderstanding of multiple voltage (HV) domains and layout techniques requiredCustom analog layout experience should include various analog IP blocks: PLLs, OSC, ADC, DAC, LDO and Bandgap referenceExcellent communication skills and ability to work with cross-functional teams in a demanding team-oriented environmentSelf-starter and self-sufficient in problem solving and accomplishing tasksExperience with Analog design is highly appreciatedScripting experience in PERL or SKILL CODE is considered a plus, but not required  For more information and to apply, please click APPLY NOW to speak to a member of the team.