This is an exciting opportunity for a Digital Design Engineer to join my client in one of three locations in France. This is a superb opportunity to join a dynamic design team and be instrumental in the design, architecture definition and verification of ASIC sub blocks.
Located in either the busy and lively city of Paris or the beautiful town of Sophia Antipolis this is a role which will suit a budding engineer with a few years experience and gives the opportunity for growth and career succession.
I am seeking a motivated digital design engineer with a masters or PhD and a minimum of 3 years experience in micro-architecture definition, RTL design and verification. This role requires the successful candidate to have a solid background in digital electronic and signal processing as well as solid knowledge of digital hardware description languages VHDL or Verilog and scripting languages including Perl, TcL or Python.
The successful Digital Design Engineer will spend time working on the specifications and definition of the Micro-architecture of digital sub blocks alongside RTL deign and should be able to elaborate detailed verification plans corresponding to circuit definitions, so experience in UVM methodology would be advantageous. You must have previous experience with Cadence or Synopsys and you must be able to read and write in English.
This role requires the engineer to have French working rights.
For more information and a detailed discussion contact Rachel Click here to contact this recruiter Resources.
Contact Name: Rachel Mason
Job ID: 2776390