|Listed on:||21st November|
|Location:||Republic of Ireland|
|Contact Name:||Ane Bauer|
A world renown wireless company is looking for an IC Mask Layout Engineer to join their team in Ireland to contribute to leading edge 5G products and technologies.
This role involves the integration of Macro Layouts from 3rd Party vendors into cutting edge designs. The successful applicant will be responsible for providing support for 3rd party hard and soft macros in the company flow including providing custom collaterals like bumps and RDR rules and others to the vendor, importing the design database into the companies own flow, performing physical checks (DRC/LVS/ERC/PERC) and the resolution of any issues arising from this.
You will be required to debug any physical verification violations observed working closely with the IP vendor to resolve these, generate any IP views not supported by the vendor, and work closely with the hard macro and SoC teams to resolve any IP level integration issues encountered in the design hierarchy.
As the successful IC Mask Layout Engineer you have solid experience with layout design and debug in FinFet technologies as well as prior experience with management, QA, or support of GDSII and/or OASIS databases and the Cadence Virtuoso, Calibre RVE, Calibre DRV, Perl.
This is an excellent opportunity for an Analog IC Layout Engineer to join on of the world leader in the development of 5G.
For more information about the role and the company and to discuss your expectations, please contact Ane at IC Resources with your CV and a time for a first call.