Analog IC Design Engineer - PLLs
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An opportunity has arisen for an experienced Analog IC Design Engineer to join an expanding company based in the French speaking part of Switzerland. In this position you will be responsible for the Design of next generation PLLs for high speed links (SerDes) in CMOS technology.Responsibilities include:Investigation and design of PLL architecturesValidation of PLL sub-blocksDesign of transistor schematics of PLL's and all component sub-blocksVerification of top level PLLsSupervision of physical design to ensure high performance PLL layoutLab and ATE test plans and measurement for characterisationIndustry degree qualified, the successful Analog IC Design Engineer will have a thorough understanding of advanced PLL architectures, including LC PLLs, hybrid PLLs, all-Digital PLLs. Familiarity with PLL modelling in languages such as Matlab, Python, C++ or similar is required along with strong experience in transistor level design and layout of key PLL building blocks, such as VCOs, charge-pumps and high-speed frequency dividers. It would be advantageous to have experience on modern process nodes down to 28nm, 14nm, 16nm or 7nm. Strong design and verification tools experience is required including Virtuoso, Maestro, Spectre, to design and verify PLL performance as well as ensuring meeting reliability goals.The successful applicant will be self motivated with strong sense of ownership and responsibility. You will have excellent communication skills and be a strong team player you will be able to work well within a multi-site team.Contact Leon at IC Resources to find out more and to apply.