Senior Analog IC Layout Engineer

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You are looking to a position in Analog IC Layout that allow you to grow into a Teamleader/Manager?

A leader in the development of DRAM products is looking for a layout engineer to join their team in Munich to develop full-custom layouts of complex, high-speed Analog IC's and integrate the full-custom blocks into a semi-custom design flow and set-up the corresponding CAD environment. Collaboration with and guidance of layout and engineering teams across different international sites.

Your responsibilities include the following:

- Full-custom layout of CMOS high speed Analog ICs such as transmitter, receiver, PLL and full speed sections of the data path in Cadence Virtuoso

- Floorplanning on cell, block and chip level

- LVS/DRC/ERC verification

- RC extraction and EM analysis

- Collaboration with and guidance of international development teams

- Participation in methodology development and flow improvement

The successful Layout Engineer will have:

- At least 5 years experience in high-speed analog block layout, including floor planning, power routing and full verification prior to tape-out.

- Good understanding of the layout impact on IC behaviour, matching, noise, coupling, shielding and IR-drop

- Knowledge of CAD tools (Cadence)

- Fluent English skills