Graphics Design Verification Lead

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Job Summary

Do your life’s best work here. With the whole world watching. At Apple, great ideas and even complex challenges have a way of becoming great products, services, and customer experiences very quickly. This is a career defining opportunity to get in at the ground floor as we start up our UK team. Working with our Engineering teams in the US & Worldwide, you will work alongside world-class experts who are responsible for driving the direction of technological innovation across the globe. The Graphics Verification Lead will be responsible for a team owning the pre-silicon RTL verification of blocks in graphics cores. This includes deep understanding of the micro-architectural details of designs and how they work within the broader GPU. A strong computer architecture background, preferably in graphics, and a solid foundation in verification methodology will be leveraged to close testing coverage with high confidence.

Key Qualifications

- The ideal candidate will have multiple years of relevant experience including:

- Previous success owning DV for a complex GPU block and leading a DV team

- Expertise with a verification language such as SystemVerilog/UVM/OVM and/or strong software engineering (C/C++) skills

- Expertise with Verilog/VHDL, HDL simulators, and waveform viewers

- Experience defining coverage space, writing coverage model, analyzing results

- Experience working under strict deadlines and managing multiple priorities

- Graphics architecture knowledge highly desired. Strong knowledge of computer architecture, general purpose microprocessor and memory sub-system micro-architecture in lieu of graphics experience

- Experience with Perl, Shell scripting, Makefiles, TCL a plus

- Excellent communication skills and ability to collaborate

Description

Full responsibility for DV of a hardware block/IP, including leading a DV team and communicating plans and status to management Develop and track to verification plans on an aggressive schedule through sign-off, in coordination with design leads, architects, and program management Create and maintain verification test bench components and environments Generate directed and directed random tests Run simulations and debug design and environment issues Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes Create automated verification flows for block verification Apply knowledge of hardware description languages (VHDL/Verilog), verification languages (SystemVerilog/UVM/OVM), and simulators to verify complex designs Work with other block and core level engineers to ensure seamless verification flow

Education

BS/MS CE or EE

Additional Requirements

Some international travel will be required.