Design Verification Engineer

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Design Verification Engineer

Location: Sophia Antipolis, Southern France

Our client, a leading telecommunication company are seeking a IP Design Verification Engineer to join the existing HiSilicon Image Signal Processor development team.

The Design Verification Engineer will work closely with imaging algorithm developers, RTL designers, other DV engineers as well as hardware and software architects.

The responsibilities of the Design Verification Engineer include;

* Write verification specification documentation

* Verification environment setup

* Integration of algorithmic and transaction level models

* Create test plans

* Test case development

* Test case execution and debug

Background from Design Verification Engineer;

* 3+ year in a Verification Engineering/Design role

* Proven track record in all phases of complex multimedia accelerator verification (test plan, verification environment, test implementation / execution / debug, test patterns, coverage, regression / automation)

* Proficient in state of the art verification strategies, automatization and progress tracking

* Experience with signal processing / multimedia hardware accelerator verification

* System Verilog, UVM, simulation flow, tcl, perl, python, C/C++

* Fluent in French and English

* Formal verification expertise is a plus

* Knowledge in image processing, image sensors, MIPI interfaces, System C modeling, FPGA prototyping, silicon validation are a plus

Key: Design Verification Engineer, IP, HiSilicon, EnSilicon, EnSilica, DSP, VIP, AVS, AVK, ASIC, IC, 0033, +33, France, R&D, Research, Innovation