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SoC DFT Engineer - ASIC, DFT
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| Location: | Hertfordshire east of england | hertfordshire |
|---|---|
| Tags: | asic | ic | vhdl | digital | verilog | engineering | validation | analogue | asic east of england | asic hertfordshire |
| Type: | Permanent |
Our client seeks a DFT Engineer with skills in some/ all of the following: digital, IC, ASIC, FPGA, RTL, VHDL, Verilog, Design for Test, DFT, verification, synthesis, layout, BIST, boundary scan, mux-scan, test, debug, SoC, architecture, clocking, semiconductor.
International semiconductor company seeks a DFT Engineer to join a team taking multi-million gate designs from specification through to GDSII, using a mix of internal and third party IP. This position requires a sound knowledge of the complete digital ASIC design flow (130nm and below) and will involve:
DFT architecture and implementation including mux-scan, memory BIST, boundary scan, test structures for analogue macros, test structure validation, test vector generation and debug. The role will also involve exposure to a range of other SoC integration activities.
Suitable candidates will be degree qualified in Electronic Engineering or related subject, and be skilled in the following areas:
·Design for Test
·RTL design (VHDL and/ or Verilog)
·Synthesis and timing optimisation (block and full chip)
·Formal verification (RTL to gates, gates-to-gates)
·Low power design techniques (ideal but not essential)
<i>'IC Resources - your first contact for ASIC / FPGA positions throughout the UK, Europe and worldwide. Deep market knowledge and extensive contacts. Personal representation, strong ethics.' www.ic-resources.co.uk </ i>
International semiconductor company seeks a DFT Engineer to join a team taking multi-million gate designs from specification through to GDSII, using a mix of internal and third party IP. This position requires a sound knowledge of the complete digital ASIC design flow (130nm and below) and will involve:
DFT architecture and implementation including mux-scan, memory BIST, boundary scan, test structures for analogue macros, test structure validation, test vector generation and debug. The role will also involve exposure to a range of other SoC integration activities.
Suitable candidates will be degree qualified in Electronic Engineering or related subject, and be skilled in the following areas:
·Design for Test
·RTL design (VHDL and/ or Verilog)
·Synthesis and timing optimisation (block and full chip)
·Formal verification (RTL to gates, gates-to-gates)
·Low power design techniques (ideal but not essential)
<i>'IC Resources - your first contact for ASIC / FPGA positions throughout the UK, Europe and worldwide. Deep market knowledge and extensive contacts. Personal representation, strong ethics.' www.ic-resources.co.uk </ i>
http://www.technojobs.co.uk/job.phtml/152370
