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Physical Design / IC Layout Engineers - Italy

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Location:Italy
Tags: ic | digital | asic |
Type:Permanent
New vacancies exist for physical design engineers to be based in Italy. Skills include: digital, physical, IC, SoC, Layout, back end, timing analysis, STA, static timing analysis, place and route, P&R, PNR, floorplanning, 90nm, clocktree synthesis, signal integrity, physical verification, tapeout, semiconductor.

Europe's leading design consultancy requires several physical design engineers with particular experience in timing closure.

We are looking for motivated, flexible individuals who are able to make frequent trips to customer sites throughout Europe. There is also the option for some home working when travel is not required.

This role can be based in Milan. Candidates must be degree qualified in a relevant subject, with strong experience in chip level timing analysis. Previous experience of chip level timing analysis work essential, familiarity with crosstalk timing and signal integrity issues all desirable. Knowledge of 90nm design flows and methods would be an advantage.

Please contact IC Resources for further details.

<i>'IC Resources - your first contact for ASIC / FPGA positions throughout the UK, Europe and worldwide. Deep market knowledge and extensive contacts. Personal representation, strong ethics.' www.ic-resources.co.uk </ i>

http://www.technojobs.co.uk/job.phtml/150489

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